Fast Fourier transformation (FFT) is a powerful analytical tool with wide-ranging applications in many fields. The standard FFT algorithms inherently assume that the length of the input and output sequence are equal. In practice, it is not always an accurate assumption. In certain case only some of the inputs to the transformation function are non-zero but lot of other are zero. In this thesis, a novel architecture of a 1024-point FFT, which adopts the transform decomposition (TD) algorithm, is presented to further reduce the complexity when the non-zero input data are consecutive. To implement this FFT processor, fixed point simulation is a conducted by using MATLB. The hardware implementation is realized by using the Verilog Hardware Description Language (HDL) which is taped out in TSMC0.18 Cell-Based Library for system verification.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0826108-052816 |
| Date | 26 August 2008 |
| Creators | Wu, Jian-Shiun |
| Contributors | Jyh-Horng Wen, Shyue-Win Wei, Tsang-Yi Wang, Chih-Peng Li, Chau-Chin Wang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0826108-052816 |
| Rights | not_available, Copyright information available at source archive |
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