A circuit design of Fast Fourier Transform for DVB-H system is presented in this thesis. This circuit is based on SDF (single path delay feedback) pipeline architecture with radix-2 computation element. We propose a novel method of timing scheduling that can share one complex multiplier for couple of stage and promote the utilization of complex multiplier to 100%, so we can improve the implementation with radix-2 computation. The number of bits is carefully selected by system simulation to meetthe requirements of DVB-H system. In addition, a memory table permutation deletion method for memory scheduling, which can reduce the size of memory storing twiddle factors tables.
The circuit is carried out by CMOS 0.18£gm 1P6M process with core area 2.08 x 2.076 mm2. In the gate level simulation, the output data rate of this circuit is above 50MHz, so the circuit can meet the requirement of DVB-H system.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0305109-172332 |
| Date | 05 March 2009 |
| Creators | Tseng, Wei-Chen |
| Contributors | Ching-Piao Hung, Ju-Ya Chen, Jih-Ching Chiu, Chin-Der Wann |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0305109-172332 |
| Rights | not_available, Copyright information available at source archive |
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