Doctor of Philosophy / Department of Industrial & Manufacturing Systems Engineering / Zhijian Pei / Silicon is the primary semiconductor material used to fabricate integrated circuits (ICs). The quality of integrated circuits depends directly on the quality of silicon wafers. A series of processes are required to manufacture the high-quality silicon wafers.
Chemical mechanical polishing is currently used to manufacture the silicon wafers as the final material removal process to meet the ever-increasing demand for flatter wafers and lower prices. A finite element analysis has been conducted to study the effects of influencing factors (including Young's modulus and Poisson's ratio of the polishing pad, thickness of the pad, and polishing pressure) on the wafer flatness. In addition, an experimental study was carried out on the effects of process variables (including wafer rotation speed, pad rotation speed, the temperature of the cooling wafer in polishing table, polishing pressure, and the slurry flow rate) on material removal rate (MRR) in polishing of silicon wafers. The results from this study show that the polishing pressure and the pad speed are the most significant factors affecting the MRR.
The polishing pad is one of the most critical factors in planarizing the wafer surface. It transports the slurry and interacts with the wafer surface. When the number of polished wafers increases, the pad is glazed and degraded and hence the polishing quality is decreased. The pad properties are changed during the process. The measuring methods for the pad properties including pad thickness monitoring, elastic properties and hardness are reviewed. Elasticity of two types of pads are measured and compared.
The poor flatness problems such as tapering, edge effect, concave or convex wafer shape were investigated. Finite element models were developed to illustrate the effects of polishing pad and carrier film properties on the stress and contact pressure distribution on the wafer surface. Moreover, the material removal unevenness is studied.
A grinding-based manufacturing method has been investigated experimentally to demonstrate its potential to manufacture flat silicon wafers at a lower cost. It has been demonstrated that the site flatness on the ground wafers (except for a few sites at the wafer center) could meet the stringent specifications for future silicon wafers. One of the problems is the poor flatness at the wafer center: central dimples on ground wafers. A finite element model is developed to illustrate the generation mechanisms of central dimples. Then, effects of influencing factors (including Young's modulus and Poisson's ratio of the grinding wheel segment, dimensions of the wheel segment, grinding force, and chuck shape) on the central dimple sizes are studied. Pilot experimental results are presented to substantiate the predicted results from the finite element model. This provides practical guidance to eliminate or reduce central dimples on ground wafers.
The study in this thesis is to understand the mechanism of CMP and grinding of silicon wafers. Improving the processes and the quality of silicon wafers are the final goals.
| Identifer | oai:union.ndltd.org:KSU/oai:krex.k-state.edu:2097/475 |
| Date | January 1900 |
| Creators | Zhang, Xiaohong |
| Publisher | Kansas State University |
| Source Sets | K-State Research Exchange |
| Language | en_US |
| Detected Language | English |
| Type | Dissertation |
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