An early evaluation in terms of circuit design is essential in order to assess the feasibility and practicability aspects for emerging nanotechnologies. Reconfigurable nanotechnologies, such as silicon or germanium nanowire-based reconfigurable field-effect transistors, hold great promise as suitable primitives for enabling multiple functionalities per computational unit. However, contemporary CMOS circuit designs when applied directly with this emerging nanotechnology often result in suboptimal designs. For example, 31% and 71% larger area was obtained for our two exemplary designs. Hence, new approaches delivering tailored circuit designs are needed to truly tap the exciting feature set of these reconfigurable nanotechnologies. To this effect, we propose six functionally enhanced logic gates based on a reconfigurable nanowire technology and employ these logic gates in efficient circuit designs. We carry out a detailed comparative study for a reconfigurable multifunctional circuit, which shows better normalized circuit delay (20.14%), area (32.40%), and activity as the power metric (40%) while exhibiting similar functionality as compared with the CMOS reference design. We further propose a novel design for a 1-bit arithmetic logic unit-based on silicon nanowire reconfigurable FETs with the area, normalized circuit delay, and activity gains of 30%, 34%, and 36%, respectively, as compared with the contemporary CMOS version.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:76812 |
| Date | 26 November 2021 |
| Creators | Rai, Shubham, Trommer, Jens, Raitza, Michael, Mikolajick, Thomas, Weber, Walter M., Kumar, Akash |
| Publisher | IEEE |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English, German |
| Detected Language | English |
| Type | info:eu-repo/semantics/acceptedVersion, doc-type:article, info:eu-repo/semantics/article, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | 1557-9999, 10.1109/TVLSI.2018.2884646 |
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