In our thesis, we develop a modified fabrication method based on Ge condensation mechanism to fabricate SGOI (SiGe-on-insulator) Wafer. The advantages of this technique are as follows;
(1) Low fabrication temperature.
(2) Smooth SiGe/SiO2 interface without using CMP and good crystal quality.
(3) Better gate dielectric layer quality by dry oxidation.
In our experiment, we use silicon wafer rather than the SOI wafer to avoid cost because of the high price of the SOI wafer. First, a 700Å Si0.85Ge0.15 layer was grown on a thin SOI layer. The Ge atoms were rejected from the oxidized layer and pushed into the remaining SiGe layer by using dry oxidation at 925¢J. Since it has been confirmed that the total amount of the Ge atom in the SGOI layer is conserved, the Ge fraction can be varied from 15% to 35%. During the fabrication procedure, we use semiconductor measurement instruments like AFM /SEM /Raman spectroscopy to verify the SiGe layer quality and built complete parameters database.
Then we make two different structure Si/SiGe heterojunction MOS capacitors on this wafer to verify the necessity of the Si cap layer to SGOI substrate. According to the experiment results, we can find the device with Si cap layer has better performences than the one without Si cap about 10% ~ 20% in electric characteristics.
Based on the experiment results, it is proved that a high quality SGOI wafer on the SOI wafer can be fabricated.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0718103-085942 |
| Date | 18 July 2003 |
| Creators | Chen, Pain-Chin |
| Contributors | Jinn-Shyan Wang, Jyi-Tsong Lin, Yao-Tsung Tsai |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718103-085942 |
| Rights | unrestricted, Copyright information available at source archive |
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