Thesis submitted in partial fulfilment of the requirements for the degree
Master of Technology: Electrical Engineering
in the Faculty of Engineering
at the Cape Peninsula University of Technology
2015 / Space-borne GPS receivers designed for nano-satellites are faced with various challenges. This research is undertaken to address the problems of inefficiency and high-costs associated with space-borne GPS receivers. The problem of inefficiency relates to poor performances of the GPS receiver in terms of the algorithmic models, execution speed, memory usage and errors proness. The problem of high-costs relates to the spacegrade hardware cost, implementation complexity, development time, as well as the manufacturing, production and the testing processes involved.
The research objectives are to i) establish an efficient high-dynamics software-defined GPS receiver, ii) demonstrate a firmware approach and then iii) postulate a low-cost hardware implementation roadmap. The research methodology employed to address the problems and to attain the objectives is based-on using Matlab computing platform to i) implement a software-defined GPS receiver using free open-source GPS receiver algorithms, ii) further develop the software GPS receiver and lastly iii) convert the improved GPS receiver algorithms to firmware.
The GPS receiver was successfully implemented in Matlab floating-point algorithms with a ±100kHz Doppler search bins and was used to post-process a pre-captured real GPS L1 C/A signal dataset. The pre-captured GPS signal was acquired, tracked, decoded and post-processed to extract the navigation message; use to compute the GPS receiver position, UTC date and time.
Attempt to convert the entire Matlab floating-point GPS receiver algorithms to equivalent VHDL implementations failed; however, three of the Matlab floating-point algorithms (check_t.m, deg2dms.m and findUtmZone.m), were successfully converted to equivalent fixed-point formats in Matlab, Simulink and finally VHDL. These three algorithms, now created and optimised to fixed-point formats (efficient and enable implementation unto a low-cost microcontroller), set the basis for the firmware implementation. They were simulated and verified in Matlab, Simulink and VHDL using the Matlab HDL Coder workflow. Altera Quartus II software was then used to compile (synthesise, place & route and generate programming files) the three converted generic VHDL algorithms to embedded firmware, suitable for a FPGA programming.
The Matlab HDL Coder workflow used in this research is feasible and can be used to accurately design and implement an improved GPS receiver and furthermore achieve it in three equivalent algorithms. This conclusion was drawn and the proposed recommendations are to address the conversion issues in the other Matlab floating-point GPS receiver algorithms that failed in the conversion process and to further develop and implement the GPS receiver as a fully functional unit, based-on the Xilinx space-grade, radiation hardened and low-cost Virtex 5QV FPGA.
| Identifer | oai:union.ndltd.org:netd.ac.za/oai:union.ndltd.org:cput/oai:localhost:20.500.11838/1176 |
| Date | January 2015 |
| Creators | Bayendang, Nganyang Paul |
| Publisher | Cape Peninsula University of Technology |
| Source Sets | South African National ETD Portal |
| Language | English |
| Detected Language | English |
| Type | Thesis |
Page generated in 0.0022 seconds