The main aim of this thesis is to implement a voltage-controlled oscillator for a Galileo/GPS receiver with a center frequency of 1.5 GHz in 150 nm CMOS process. As the designed VCO has to be integrated in a phase locked loop, VCO gain is selected high enough for the PLL to lock even with process variations. A new state of art architecture called double harmonic tuned VCO is selected and designed for this GPS application. It uses a complex combination of inductors and capacitors to reduce phase-noise of the VCO by suppressing second harmonic oscillations in the tail node of VCO. The designed VCO shows significant improvement in phase-noise performance compared to a normal LC tank VCO by reducing phase-noise around 4 dBc/Hz. The VCO has a phase-noise of -128 dBc/Hz at 1 MHz offset from center frequency with a power consumption of 5 mW and a tuning range of about 257 MHz for a 1 V tuning voltage range.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-76279 |
| Date | January 2012 |
| Creators | Murugan, Deepak |
| Publisher | Linköpings universitet, Institutionen för systemteknik, Linköpings universitet, Tekniska högskolan |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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