Decisions regarding the mapping of system-on-chip (SoC) components onto a NoC become more difficult with increasing complexity of system design. These complex systems capable of providing multiple functionalities tend to operate in multiple modes of operation. Modeling the system communication in these multimodes aids in efficient system design. This research provides a heuristic that gives a flexible mapping solution of the multimode system communications onto the NoC topology of choice. The solution specifies the immediate neighbors of the SoC components
and the routes taken by all communications in the system. We validate the mapping results with a network-on-chip simulator (NoCSim). This thesis also investigates the cost associated with the interfacing of the components to the NoC. With the goal of reducing communication latency, we examine the packetization strategies in the NoC
communication. Three schemes of implementations were analyzed, and the costs in terms of latency, and area were projected through actual synthesis.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/299 |
| Date | 30 September 2004 |
| Creators | Bhojwani, Praveen Sunder |
| Contributors | Mahapatra, Rabi N. |
| Publisher | Texas A&M University |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Thesis, text |
| Format | 550657 bytes, 60458 bytes, electronic, application/pdf, text/plain, born digital |
Page generated in 0.002 seconds