Return to search

An Analysis of Approaches to Efficient Hardware Realization of Image Compression Algorithms

In this thesis an attempt has been made to develop a fast algorithm to compress images. The Reed-Muller compression algorithm which was introduced by Reddy & Pai [3] is fast, but the compression factor is too low when compared to the other methods. In this thesis first research has been done to improve this method by generalizing the Reed-Muller transform to the fixed polarity Reed-Muller form. This thesis shows that the Fixed Polarity Reed-Muller transform does not improve the compression factor enough to warrant its use as an image compression method. The paper, by Reddy & Pai [3], on Reed-Muller image compression has been criticized, and it was shown that some crucial errors in this paper make it impossible to evaluate the quality and compression factors of their approach. Finally a simple and fast method for image compression has been introduced. This method has taken advantage of the high correlation between the adjacent pixels of an image. If the matrix of pixel values of an image is divided into bit planes from the Most Significant Bit (MSB) plane to the Least Significant Bit (LSB) plane, most of the adjacent bits in the MSB planes (MSB, 2nd MSB, 3rd MSB and 4th MSB) are the same. Using this fact a method has been developed by Xoring the adjacent lines of the MSBs planes bit by bit, and Xoring the resulting planes bit by bit. It has been shown that this method gives a much better compression factor, and can be realized by much simpler hardware compared to Reed-Muller image compression method.

Identiferoai:union.ndltd.org:pdx.edu/oai:pdxscholar.library.pdx.edu:open_access_etds-5893
Date27 October 1994
CreatorsIravani, Kamran
PublisherPDXScholar
Source SetsPortland State University
Detected LanguageEnglish
Typetext
Formatapplication/pdf
SourceDissertations and Theses

Page generated in 0.002 seconds