At present the scale of multimedia and communication systems has become more and more complicated due to the fast development of them. In order to improve the capability of real-time processing and shorten system development time, the ability to reconfigure system architecture becomes an important and flexible design consideration. In this thesis, we propose a reconfigurable processing unit, FMRPU, which is a fine-grain multi-context reconfigurable processing unit targeting at high-throughput and data-parallel applications. It contains 64 reconfigurable logic arrays, 16 switch boxes, and connects with each other via three hierarchical-level connectivities. To avoid the excessive routing path to be the bottleneck of mapped circuits, we design the data stream switch to rearrange data streams. According to the simulation results, the longest routing path of FMRPU only takes 6.5 ns at 0.35 processes, which is able to construct the required logic circuit efficiently. Compare with same kind devices in dealing with Motion Estimation operations, the performance is raise to 17% and is excellent to other same kind architectures in executing other DSP algorithms.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0713104-180405 |
| Date | 13 July 2004 |
| Creators | Lin, Ren-Bang |
| Contributors | Shen-Fu Hsiao, Jih-Ching Chiu, Chung-Ping Chung |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0713104-180405 |
| Rights | off_campus_withheld, Copyright information available at source archive |
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