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Eliminating Charge Sharing in Clocked Logic Gates on the Device Level Employing Transistors with Multiple Independent Inputs

Charge sharing poses a fundamental problem in the design of dynamic logic gates, which is nearly as old as digital circuit design itself. Although, many solutions are known, up to now most of them add additional complexity to a given system and require careful optimization of device sizes. Here we propose a simple CMOS-technology compatible transistor level solution to the charge sharing problem, employing a new class of field effect transistors with multiple independent gates (MIGFETs). Based on mixed-mode simulations in a coordinated device-circuit co-design framework, we show that their underlying device physics provides an inherent suppression of the charge sharing effect. Exemplary circuit layouts as well as discussion on the switching performance are given.

Identiferoai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:79714
Date23 June 2022
CreatorsTrommer, Jens, Simon, Maik, Slesazeck, Stefan, Weber, Walter M., Mikolajick, Thomas
PublisherIEEE
Source SetsHochschulschriftenserver (HSSS) der SLUB Dresden
LanguageEnglish
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/acceptedVersion, doc-type:conferenceObject, info:eu-repo/semantics/conferenceObject, doc-type:Text
Rightsinfo:eu-repo/semantics/openAccess
Relation978-1-72811-539-9, 10.1109/ESSDERC.2019.8901730

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