This master thesis deals with the realization of a simulator based on asynchronous cellular automata simulating delay insensitive circuits. In connection with nanotechnology, cellular automata have several interesting properties, such as self-replication, regular structure and high parallelism that make them very useful as models for some types of nanocomputers. This text describes the relationship between cellular automata and nanotechnology. Emphasis is given to the possibility of using asynchronous timing mode. Asynchronous cellular arrays based on asynchronous cellular automata could prove to be a suitable architecture for future nanocomputer, which was the reason for implementation of this simulator. The simulator's functionality was verified by experiments.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:236570 |
| Date | January 2012 |
| Creators | Kmeť, Dušan |
| Contributors | Bidlo, Michal, Sekanina, Lukáš |
| Publisher | Vysoké učení technické v Brně. Fakulta informačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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