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4kb DRAM with an Temperature-Insensitive Self-Refreshing Circuitry and Fast Half-Swing NOR-NOR PLA Architecture

The first part of this thesis presents a novel design for DRAMs to provide self-refreshing cycles which vary with temperature dynamically to reduce power dissipation in a standby mode. The proposed design monitors the data loss of a memory cell which is resulted from the leakage current, and then adjusts the period of the self-refreshing cycles.
The second part presents two fast half-swing CMOS circuits for NOR-NOR PLA implementation. An additional 1/2VDD voltage source and buffering transmission gates are inserted between the NOR planes of PLAs to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0624102-214443
Date24 June 2002
CreatorsChiu, Chih-Chiang
ContributorsShen-Fu Hsiao, Sying-Jyan Wang, Chua-Chin Wang, Chi-Feng Wu
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0624102-214443
Rightsnot_available, Copyright information available at source archive

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