Return to search

Crosstalk fault test generation and hierarchical timing verification in VLSI digital circuits /

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 102-107). Available also in a digital version from Dissertation Abstracts.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/47212843
Date January 1999
CreatorsLee, Kyung Tek,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceDigital version accessible at:

Page generated in 0.0017 seconds