Jitter reduction circuits to reduce the bit-error rate of high-speed serializer-deserializer (SERDES) circuits

Description

Thesis (Ph. D.)--Rutgers University, 2008. / "Graduate Program in Electrical and Computer Engineering." Includes bibliographical references (p. 137-140).

Links & Downloads

1. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17259

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Additional Fields

Identifer	oai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/430652168
Date	January 2008
Creators	Venkatanarayanan, Hari Vijay.
Source Sets	OCLC
Language	English
Detected Language	English