Different network devices require processing of the network traffic. To process the network traffic, it is necessary to parse headers of particular protocols packed in incoming ethernet frames. The processed headers can be repackaged to ethernet frames and sent back to the network. The goal of this thesis is to design and implement a circuit for analysis and parsing of ethernet frames, together with circuit for deparsing ethernet frames. The circuits are designed for throughputs of up to 400 Gb/s. The circuits are implemented for the FPGA technology.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:318173 |
| Date | January 2017 |
| Creators | Cabal, Jakub |
| Contributors | Dvořák, Vojtěch, Fujcik, Lukáš |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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