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Improving Workload Balance and Code Optimization on Processor-In-Memory Systems

PIM (Processor-In-Memory) architectures have been proposed in recent years. One major objective of PIM is to reduce the performance gap between the CPU and memory. To exploit the potential benefits of PIM, we designed a statement base parallelizing system ¡VSAGE in [1, 2]. In order to make all processors take the best-fit workload in PIM, iteration base analysis is another research issue in this paper. We extend this system to achieve better performance by devising several comprehensive optimizing techniques, which include IMOP (Intelligent Memory Operation) recognition, tiling for PIM, and a precise mechanism to get workload balance execution schedule. The experimental results are also presented and discussed.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0614101-164407
Date14 June 2001
CreatorsLee, Lan-Chi
ContributorsChih-Ping Chu, Tsung-Chuan Huang, Nai-Wei Lin, Shian-Shyong Tseng, Yeh-Ching Chung
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614101-164407
Rightsunrestricted, Copyright information available at source archive

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