An efficient test generation algorithm for behavioral descriptions is discussed. It generates tests for behavioral dataflow descriptions of digital circuits written in VHDL. The algorithm accepts input descriptions containing multiple process statements and concurrent signal assignment statements. The fault model based on previous research includes micro-operation and control faults. The test generation algorithm uses artificial intelligence techniques of goal trees and rule databases and it can make use of human understanding of the device model to generate more efficient tests. An improved timing model helps detect conflicts more quickly and improves the speed performance of the algorithm. The test generation algorithm has been used to generate tests for complex circuits. Results of fault coverage experiments for some of these circuits is presented. / Master of Science
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/53723 |
| Date | January 1988 |
| Creators | Jani, Dhanendra Dinesh |
| Contributors | Electrical Engineering |
| Publisher | Virginia Polytechnic Institute and State University |
| Source Sets | Virginia Tech Theses and Dissertation |
| Language | en_US |
| Detected Language | English |
| Type | Thesis, Text |
| Format | viii, 104 leaves, application/pdf, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | OCLC# 19611399 |
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