<p>This Master's thesis reports the verification planning and verification process of a Verilog RTL model. Modern verification techniques like constrained randomization, assertions, functional coverage analysis and object orientation are demonstrated on an AES RTL model. The work of this thesis was naturally divided in three phases: First, a phase of literature studies to get to know the basics of verification. Second, the creation of a verification plan for the selected module. Third, implementation of the testbench, and simulation tasks. The verification plan created states the goals for the simulation. It also states plans for details about the testbench, like architecture, stimuli generation, random- ization, assertions, and coverage collection. The implementation was done using the SystemVerilog language. The testbench was simulated using the Synopsys VCS ver- ification software. During simulation, coverage metrics were analyzed to track the progress and completeness of the simulation. Assertions were analyzed to check for errors in the behavior during simulation. The analysis carried out revealed high code coverage for the simulations, and no major errors in the verified module.</p>
| Identifer | oai:union.ndltd.org:UPSALLA/oai:DiVA.org:ntnu-8704 |
| Date | January 2007 |
| Creators | Ruud, Henrik |
| Publisher | Norwegian University of Science and Technology, Department of Electronics and Telecommunications, Institutt for elektronikk og telekommunikasjon |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, text |
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