I 0.18 µm CMOS process har ett standardcells bibliotek med låg effektförbrukning implementerats. Cellerna har konstruerats och simulerats i Cadence och ett layoutprogram. Vid simulering av heladderare och D-vippor har effektförbrukningen och tider mätts upp och jämförts med varandra. Matningsspänningen varierade mellan 1 V och 1.8 V. In 0.18 µm CMOS process has a standard cell library with low power consumption been implemented. The cells have been made and simulated in Cadence and a layout program. At the simulation of the full adders and the D flip flops the power consumption and time have been estimated and compared. The power supply voltage varied between 1 V and 1.8 V. / A standard cell library with low power consumption has been implemented in a 0.18 mm CMOS process. The cells have been designed and simulated in Cadence and a layout program. During the simulation of the full adders and the D flip flops the power consumption and time have been estimated and compared. The power supply voltage varied between 1 V and 1.8 V.
Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-1917 |
Date | January 2003 |
Creators | Rasmusson, Oscar |
Publisher | Linköpings universitet, Institutionen för systemteknik, Institutionen för systemteknik |
Source Sets | DiVA Archive at Upsalla University |
Language | English |
Detected Language | English |
Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
Format | application/pdf |
Rights | info:eu-repo/semantics/openAccess |
Relation | LiTH-ISY-Ex-ET, ; 0265 |
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