In the early 1980s and 1990s, the first- and second-generation networks in wireless communication, called 1G and 2G, were introduced with only limited data connectivity in the world. The former could only transfer voices while the latter could transfer voices and messages. By the early 2000s, however, the 3G networks began working and let people have real access to the internet. The greater functionality enabled by 4G networks evolved from increased demand for higher data rates in the early 2010s. Nowadays, we are totally engaged in 4G world of LTE (Long Term Evolution) owing to the eruptive increase of mobile internet in smart phones or other mobile devices. The 5G networks are categorized into two branches according to their frequencies: (i) sub-6 GHz (700 MHz to 6 GHz) and (ii) near-millimeter wave (25 to 30 GHz). Commonly used applications are included in the sub-6 GHz, also called the Internet-of-Everything (IoE) and Internet-of-Things (IoT).
To fulfill the date rate required for 5G applications, implementing complex systems is necessary. Consequently, new challenges are imposed to implement these systems such as noise performance and output power. At the heart of these systems lie frequency synthesizers. Frequency synthesizers are used to up or down convert the carrier signal in communication systems. Phase-locked loops (PLLs) are routinely utilized for frequency synthesis in Radio Frequency (RF)/mm-wave transceivers. The main challenges to design a PLL are phase noise (PN) or jitter, as well as power consumption.
The main objective of this thesis is to carry out research on a fully integrated analog PLL fractional-N frequency synthesizer for 5G wireless communication and IoE/IoT applications in sub-6 GHz. To do this, we have studied the trends in the research of LC-VCOs (voltage-controlled oscillators) and identified the methods for going towards a low flicker-noise corner. Then, we have implemented the designed LC-VCO which is the main noise source in PLLs. In the final step we have designed the sub-blocks of the fractional-N analog frequency synthesis. The sub-blocks have been optimized to have less power dissipations. The implementation of a fully integrated analog PLL fractional-N frequency synthesizer is done in 180-nm standard CMOS technology (TSMC). It covers two frequency ranges including 2.4 to 2.48 GHz and 5 to 5.825 GHz. The phase noise at 10KHz varies between -94 dBc/Hz to -115dBc/Hz. / Thesis / Doctor of Philosophy (PhD) / The data rate in wireless, cellular communications, and wireline keeps growing by nearly 10 times per 5 years. To fulfill such date rate, implementing complex systems is necessary. Consequently, new challenges are imposed to implement these systems such as noise performance and output power. At the heart of these systems lie frequency synthesizers. Frequency synthesizers are used to up or down convert the carrier signal in communication systems. Phase-locked loops (PLLs) are routinely utilized for frequency synthesis in Radio Frequency (RF)/mm-wave transceivers. The main challenges to design a PLL are phase noise (PN) or jitter, as well as power consumption.
This dissertation aims to implement an ultra-low power and low jitter frequency synthesizer for 5G wireless communication and IoE/IoT applications in 180-nm standard CMOS technology (TSMC). An analog PLL is used in this frequency synthesizer.
| Identifer | oai:union.ndltd.org:mcmaster.ca/oai:macsphere.mcmaster.ca:11375/28960 |
| Date | January 2023 |
| Creators | Bagheri, Mohammad |
| Contributors | Li, Xun, Electrical and Computer Engineering |
| Source Sets | McMaster University |
| Language | English |
| Detected Language | English |
| Type | Thesis |
Page generated in 0.002 seconds