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Novel design of multiplier-less FFT processors

No / This paper presents a novel and hardware-efficient architecture for power-of-two FFT processors. The proposed design is based on the phase-amplitude splitting technique which converts a DFT to cyclic convolutions and additions. The cyclic convolutions are implemented with a filter-like structure and the additions are computed with several stages of butterfly processing units. The proposed architecture requires no multiplier, and comparisons with other designs show it can save up to 39% total equivalent gates for an 8-bit 16-point FPGA-based FFT processor.

Identiferoai:union.ndltd.org:BRADFORD/oai:bradscholars.brad.ac.uk:10454/3129
Date January 2007
CreatorsShepherd, Simon J., Noras, James M., Zhou, Yuan
Source SetsBradford Scholars
LanguageEnglish
Detected LanguageEnglish
TypeArticle, No full-text in the repository

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