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Parallel processing and VLSI design: A high speed efficient multiplier

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Identiferoai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:ohiou1183753328
Date January 1985
CreatorsDandu, Venkata Satyanarayana Raju
PublisherOhio University / OhioLINK
Source SetsOhiolink ETDs
LanguageEnglish
Detected LanguageEnglish
Typetext
Sourcehttp://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183753328
Rightsunrestricted, This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.

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