Guarded evaluation is a power reduction technique that involves
identifying sub-circuits (within a larger circuit) whose inputs can be
held constant (guarded) at specific times during circuit operation,
thereby reducing switching activity and lowering dynamic power. The
concept is rooted in the property that under certain conditions, some
signals within digital designs are not "observable" at design
outputs, making the circuitry that generates such signals a candidate
for guarding.
Guarded evaluation has been demonstrated successfully
for custom ASICs; in this work, we apply the technique to FPGAs. In
ASICs, guarded evaluation entails adding additional hardware to the
design, increasing silicon area and cost. Here, we apply the technique
in a way that imposes minimal area overhead by leveraging existing
unused circuitry within the FPGA. The LUT functionality is modified
to incorporate the guards and reduce toggle rates.
The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's
inputs can be held constant without impacting the larger
circuit's functional correctness. We propose a simple solution to
this problem based on discovering gating inputs using "non-inverting paths"
and trimming inputs using "partial non-inverting paths" in the
circuit's AND-Inverter graph representation.
Experimental results show that guarded evaluation can reduce switching activity by
as much as 32% for FPGAs with 6-LUT architectures and 25% for 4-LUT architectures, on
average, and can reduce power consumption in the FPGA interconnect by
29% for 6-LUTs and 27% for 4-LUTs. A clustered architecture with four LUTs to a cluster
and ten LUTs to a cluster produced the best power reduction results.
We implement guarded evaluation at various stages of the FPGA CAD flow and analyze the reductions. We implement
the algorithm as post technology mapping, post packing and post placement optimizations. Guarded Evaluation
as a post technology mapping algorithm inserted the most number of guards and hence achieved the highest activity
and interconnect reduction. However, guarding signals come with a cost of increased fanout and stress on routing
resources. Packing and placement provides the algorithm with additional information of the circuit which is leveraged
to insert high quality guards with minimal impact on routing. Experimental results show that post-packing
and post-placement methods have comparable reductions to post-mapping with considerably lesser impact on the critical
path delay and routability of the circuit.
| Identifer | oai:union.ndltd.org:WATERLOO/oai:uwspace.uwaterloo.ca:10012/6644 |
| Date | January 2012 |
| Creators | Ravishankar, Chirag |
| Source Sets | University of Waterloo Electronic Theses Repository |
| Language | English |
| Detected Language | English |
| Type | Thesis or Dissertation |
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