This thesis documents the design and analysis of a low-power integrated ultra-wideband (UWB) receiver that is well suited for usage in medium to low rate, location aware communication systems. For the first time, this receiver design explores and exploits the unique properties of UWB pulse technology. By exploiting low emission power limit and pulse based communication, RF circuits have been designed with reduced linearity to achieve low-power operation and better circuit performance. The receiver design in this thesis follows a top-down approach which begins by focusing on UWB-specific issues such as signal characteristics, modulation schemes, potential advantages, and design challenges. Next, different receiver architectures are evaluated in terms of their circuit complexity, power consumption, and levels of integration. The impact of various analog non-idealities on the performance of UWB systems is also analysed in detail. After evaluating the performance of UWB systems operating with non-linear frontends, the use of pulse doublets is introduced, for the first time, to mitigate nonlinearityinduced distortion. Simulation results demonstrate that under non-linear operating conditions, significant BER improvements can be achieved by using filtering, pulse doublet, and direct sequence spread spectrum techniques. When ADC quantization effects are included in the receiver, analysis shows that quantization noise dominates distortion-induced BER degradation when two or three bits ADCs are employed. Consequently, reduced front-end linearity requirements can be tolerated in exchange for improvements in the more critical circuit parameters of the UWB receiver. By adopting the sub-linear circuit design approach, a direct-conversion receiver prototype is implemented in the 0.5 um SOS CMOS technology according to specifications determined from system-level Simulink simulations. This highly integrated receiver prototype contains a low-noise amplifier, a 4-GHz frequency synthesizer, mixers, baseband amplifiers and filters, and 2-GSps two-bit analog-to-digital converters. The receiver prototype consumes 75-mW of power, the lowest amount for reported UWB receivers operating in the 3.1 to 10.6-GHz band. Complete end-to-end simulations of the system are performed in Simulink, revealing an achievable BER of approximately 8x10e-4 Finally, a novel 79-uW 5.6-GHz CMOS frequency divider with on-chip temperature and processing compensation have been designed. The divider, designed in a 0.25 um SOS-CMOS technology, occupies 35 x 25 um2 and achieves an operating frequency of 5.6-GHz while consuming 79-uW at a supply voltage of 0.8V. The power efficiency of 143-GHz/mW is one of the highest achieved among conventional CMOS dividers. When combined with a simple and effective compensation submodule, the proposed divider is shown to achieve process and temperature-insensitive operation in a 5-GHz UNII band frequency synthesizer.
| Identifer | oai:union.ndltd.org:ADTP/242163 |
| Date | January 2006 |
| Creators | Lu, Ivan Siu-Chuang, Computer Science & Engineering, Faculty of Engineering, UNSW |
| Publisher | Awarded by:University of New South Wales. Computer Science and Engineering |
| Source Sets | Australiasian Digital Theses Program |
| Language | English |
| Detected Language | English |
| Rights | Copyright Ivan Siu-Chuang Lu, http://unsworks.unsw.edu.au/copyright |
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