This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading
channels and general AWGN channels. A model of a memory-efficient low-power
high-throughput multi-rate array LDPC decoder as well as its FPGA implementa-
tion results is first presented. Then, I propose a decoding scheme that provides the
feature of constant-time decoding and thus facilitates real-time applications where
guaranteed data rate is required. It pre-analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. The
results are then used to dynamically adjust decoder frequency and switch between
multiple-voltage levels; thereby energy use is minimized. This is in contrast to the
conventional fixed-iteration decoding schemes that operate at a fixed voltage level
regardless of the quality of data received. Analysis shows that the proposed decoding
scheme is widely applicable for both two-phase message-passing (TPMP) decoding
algorithm and turbo decoding message passing (TDMP) decoding algorithm in block
fading channels, and it is independent of the specific LDPC decoder architecture. A
decoder architecture utilizing our recently published multi-rate decoding architecture
for general AWGN channels is also presented. The result of this thesis is a decoder
design scheme that provides a judicious trade-off between power consumption and
coding gain.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-2504 |
| Date | 15 May 2009 |
| Creators | Wang, Weihuang |
| Contributors | Choi, Gwan |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Thesis, text |
| Format | electronic, application/pdf, born digital |
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