It has been confirmed that reconfigurable computing system has potential to accelerate in large amounts of data computing. However, current trend is towards combining a microprocessor with one or many reconfigurable computing units. Thus, it might cause multiple devices to compete for System Bus that caused bus collision. And then the system performance will be limited on the bandwidth. Based on these shortcomings, this paper proposes an architecture which combines DDRx memory with a reconfigurable FPGA to construct a module with both storage and computing functions called Brain module. Brain module¡¦s instruction set is created through the extension of DDRx memory instruction. We also design the brain module controller and Hardware Management Unit. According to the definition of Software-Hardware Co-communication, the dynamically constructed Hardware Management Unit will create a hardware function call mechanism. We also establish internal data switching mechanism to achieve transmission data between memory and reconfigurable computing internal the controller. Thus, it can reduce the workload of System Bus and integrate hardware and software work. In software structure, we inherit the traditional programming language and integrate program data area and reconfigurable computing data area. Brain module data is accessed through memory mapping I/O. User can implement the software-hardware co-work by integrated programming environment,
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0824111-172812 |
| Date | 24 August 2011 |
| Creators | Chen, Juei-Tsung |
| Contributors | Wann-Yun Shieh, Shen-Fu Hsiao, Jih-Ching Chiu, Chung-Ping Chung |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-172812 |
| Rights | unrestricted, Copyright information available at source archive |
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