Microelectronic systems packaging involves layout dimensions of the order of microns. During manufacturing, process variations will cause parameters to deviate from their nominal values. As a result, the manufactured circuit may no longer meet the specifications it is designed to satisfy. When producing high volume of electronics, assembly yield becomes very important. This is where tolerance margins of the design parameters play an important role. This means that the performance specifications should be satisfied if the process variations are within the given tolerance margin of design parameters.
Research has been done on circuit level design for manufacturability methods. The main objective of the research is to study the layout level DFM methods for signal integrity issues and embedded Rf passive components and use design centering methodology to improve the output yield value. In this dissertation, emphasis is also laid on taking care of the regression error while calculating the yield value. With the developed method, the number of design iteration cycles to maximize yield is significantly reduced.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/26701 |
| Date | 19 November 2008 |
| Creators | Doppalapudi, Ranjeeth |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Thesis |
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