Goal of the diploma thesis is a design of fast memory module and to introduce myself with issues involved in data storage in memory of high speed camera. The work is concerned about two designs adding memory capacity of high speed camera with DDR3 memory modules. For production is selected the more suitable design that is better for commercial purposes. The main objective is to design a schematic with FPGA as a main controller, that will operate data flow from CMOS sensor to superior development board MicroZed. Final design should allow us to sell the high speed camera as a separate unit.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:318190 |
| Date | January 2017 |
| Creators | Trtílek, Jakub |
| Contributors | Šteffan, Pavel, Musil, Vladislav |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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