Return to search

Design and Optimization of Components in a 45nm CMOS Phase Locked Loop

A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.

Identiferoai:union.ndltd.org:unt.edu/info:ark/67531/metadc5397
Date12 1900
CreatorsSarivisetti, Gayathri
ContributorsMohanty, Saraju P., Kougianos, Elias, Mikler, Armin R.
PublisherUniversity of North Texas
Source SetsUniversity of North Texas
LanguageEnglish
Detected LanguageEnglish
TypeThesis or Dissertation
FormatText
RightsUse restricted to UNT Community, Copyright, Sarivisetti, Gayathri, Copyright is held by the author, unless otherwise noted. All rights reserved.

Page generated in 0.0025 seconds