The continuously growing throughput in wireless applications severely impacts the architecture and design of modern transceivers. One of the most challenging aspects is the design of the power amplifier (PA). Indeed, this block dominantly determines the overall transceiver power efficiency and therefore battery life-time. On the other hand, PA linearity is a key feature that limits the maximum allowed data rate. The goal of this thesis is to investigate and design novel smart architectures circumventing the stringent linearity/efficiency trade-off for third generation cellular and data transmission standards. A demonstrator has been developed on silicon (0.25µm BiCMOS ST Microelectronics technology), and has allowed validating the efficiency/linearity improvement principle. / Abstract
| Identifer | oai:union.ndltd.org:theses.fr/2009BOR13901 |
| Date | 27 November 2009 |
| Creators | Leyssenne, Laurent |
| Contributors | Bordeaux 1, Kerhervé, Eric, Deval, Yann |
| Source Sets | Dépôt national des thèses électroniques françaises |
| Language | English |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation, Text |
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