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3D packaging of multi-stacked flip chips with plugged through silicon vias for vertical interconnection /

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2006. / Includes bibliographical references (leaves 97-107). Also available in electronic version.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/76075959
Date January 2006
CreatorsHon, Chi Kwong.
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceView abstract or full-text.

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