Multiple-input multiple-output (MIMO) is a well-known technique for efficiently increasing bandwidth utilization. However, the implementation of the MIMO receiver with a reasonable hardware cost is a big challenge. Most MIMO receivers exploit minimum mean-square error (MMSE), zero-forcing (ZF) and maximum-likelihood (ML) to detect MIMO signals. Among the detectors, the ZF detector is simple detector with low computational complexity, but lower performance compared to ML decoder, which has huge computational complexity. If the K-Best sphere decoding algorithm (SDA) is adopted, the system complexity can be substantially reduced and the performance can approach that of the ML scheme when the value K is sufficiently large. In this paper, a hard-output MIMO detector is implemented using the K-Best SDA for 4¡Ñ4 64-quadrature amplitude modulation (QAM) MIMO detection. The implementation is realized by using a 0.18-£gm CMOS technology. The implementation chip core area is 3.35mm2 with 229K gates, and the decoding throughput is up to 3.12Mb/s with a 25MHz clock rate.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0807108-141209 |
| Date | 07 August 2008 |
| Creators | Su, Chih-Tseng |
| Contributors | Shyue-Win Wei, Chua-Chin Wang, Chih-Peng Li, Tsang-Yi Wang, Jyh-Horng Wen |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-141209 |
| Rights | campus_withheld, Copyright information available at source archive |
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