With the rapid progress in manufacturing technology, the chip design is more and more complicated day by day. As a result, the circuit design with standard cell library becomes more significant. Standard cell is universally applied to cell-based design and the designer can complete their design quickly by using of the elements in standard cell library through cell-based design flow. Therefore, it is indispensable for VLSI design to utilize standard cell library for circuit design. Moreover, the low power design is getting increasingly important in the circuit design. Therefore, we design the cells with particular function and add them into the standard cell library so that the low power design can be more well-designed.
In this thesis, we design and and the transmission gate into the standard cell library. In addition, we design two types of standard cells with TSMC 0.13£gm technology: a low-overhead latch and a modified transmission-gate based full adder. They are applied to design different low power multipliers with cell-based design flow and full custom design flow. Experimental results show that our proposed standard cells can reduce the power consumption of the entire multiplier efficiently.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0730109-174550 |
| Date | 30 July 2009 |
| Creators | Wu, Zong-Lin |
| Contributors | Ko-Chi Kuo, Shiann-Rong Kuang, Shen-Fu Hsiao, Jer-Min Jou |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730109-174550 |
| Rights | unrestricted, Copyright information available at source archive |
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