In high-speed digital circuits, in order to utilize the space of printed circuit boards(PCB) efficiently, the signal via is a heavily used interconnection structure to communicate different signal layers. However, because of vias are small and irregular structure in the PCB. When we try to simulate these problems with traditional FDTD method. We must using more fine grid to approximate the structure, so it will take a lot CPU memory and computing times. In this author, we try to combine FDTD and FVTD method. Take FVTD method in these partial small structure and magnify grid in a ratio. Finally, combine the larger FDTD grid to achieve reducing the numbers of grids that will save CPU memory and raise computing speed. In addition, we will present another solution that shifting via to replace using small size via based on a method that is using cascaded EBG structure achieve broadband effects to cost down.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0726110-120426 |
| Date | 26 July 2010 |
| Creators | Chen, Chan-Yi |
| Contributors | Chie-In Lee, Ken-Huang Lin, Chih-Wen Kuo |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726110-120426 |
| Rights | campus_withheld, Copyright information available at source archive |
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