In this thesis, a pass-transistor logic synthesizer is developed for logic mapping of any combinational circuits based on only two types of cells: 2-to-1 multiplexors and inverters. The input contains several sum-of-product Boolean function expressions. Our synthesizer will consider the hardware sharing among these Boolean functions in order to save area. The output of our synthesizer is pass-transistor-based circuits with optimized transistor width in terms of user-specified speed and power performance measurement. During optimization, the Elmore RC delay model is used to estimate the critical path delay and the power is characterized by the switching of all the internal nodes. The final outputs are HSPICE netlists and Verilog gate-level code that allow more detailed timing simulation and automatic placement-routing.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0828101-143717 |
| Date | 28 August 2001 |
| Creators | Chen, Jian-Hung |
| Contributors | Shen-Fu Shiao, Yun-Nan Chang, Ing-Jer Huang, Yean-Kang Lai |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0828101-143717 |
| Rights | unrestricted, Copyright information available at source archive |
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