The primary design goal of many embedded systems for multimedia applications is usually meeting the performance requirement at a minimum cost. In this thesis, we proposed two different ILP based approaches for hardware/software (HW/SW) partitioning and pipelined scheduling of embedded systems for multimedia applications. One ILP approach solves the HW/SW partitioning and pipelined scheduling problem simultaneously. Another ILP approach separates the HW/SW partitioning and pipelined scheduling problem into two phases. The first phase is focusing on the HW/SW partitioning and mapping problem. Second phase is used to solve the pipelined scheduling problem. The two ILP approaches not only partition and map each computation task of a particular multimedia application onto a component of the heterogeneous multiprocessor architecture, but also schedules and pipelines the execution of these computation tasks while considering communication time. For the first ILP model, the objective is to minimize the total component cost and the number of pipeline stages subject to the throughput constraint. In the second ILP approach, the objective of the first phase and second phase is to minimize the total component cost and the number of pipeline stages subject to the throughput constraint, respectively.
Finally, experiments on three real multimedia applications (JPEG Encoder, MP3 Decoder, Wavelet Video Encoder) are used to demonstrate the effectiveness of the proposed approaches.
Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0801105-185200 |
Date | 01 August 2005 |
Creators | Chen, Chin-Yang |
Contributors | Jer-Min Jou, Shiann-Rong Kuang, Ko-Chi Kuo, Ing-Jer Huang, Shen-Fu Hsiao |
Publisher | NSYSU |
Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
Language | English |
Detected Language | English |
Type | text |
Format | application/pdf |
Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801105-185200 |
Rights | not_available, Copyright information available at source archive |
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