Diploma thesis deals with design of verification environment for analyzing systems with digital filters. Verification environment is written in SystemVerilog language and it is generated by program, which is also providing generation of input data for system of filters. Matlab environment is used for gaining the reference data. The simulation of the designed involvement with digital filters is performed by program ModelSim. The most watched parameter is functional coverage which indicates how big part of the HDL description has been tested.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:242188 |
| Date | January 2016 |
| Creators | Tesařík, Jan |
| Contributors | Dvořák, Vojtěch, Pristach, Marián |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
Page generated in 0.0014 seconds