The emerging passive optical network (PON) requires the burst mode clock and data recovery (BM-CDR) for the successful data detection, with a strict requirement in the locking time. Two innovative BM-CDR schemes are proposed, modeled, simulated, and analyzed. They simplify the circuit design and reduce the chip size and the power consumption by utilizing the characteristics of the optical components in the upstream fiber link. One scheme utilizes the phenomenon of the clock tone generation by the fiber dispersion. The other scheme utilizes the nonlinear relaxation oscillation of the directly modulated laser (DML) to generate the clock tone. The phenomenon of the clock tone generation by the DML relaxation oscillation is discovered for the first time. Both schemes do not incur extra cost, additional optical components or electrical circuit blocks. In both schemes, the BM clock recovery (CR) circuitry is based on the injection locked oscillator (ILO). Its behavior in the BM-CR application with the input of the distorted non-return-to-zero (NRZ) data is simulated at the system level for the first time. The BM-CR circuitry is designed and fabricated in a standard 0.18 !lm CMOS technology to experimentally demonstrate the two schemes operating at the bit rate close to 10 Gbps. / The emerging passive optical network (PON) requires the burst mode clock and data recovery (BM-CDR) for the successful data detection, with a strict requirement in the locking time. Two innovative BM-CDR schemes are proposed, modeled, simulated, and analyzed. They simplify the circuit design and reduce the chip size and the power consumption by utilizing the characteristics of the optical components in the upstream fiber link. One scheme utilizes the phenomenon of the clock tone generation by the fiber dispersion. The other scheme utilizes the nonlinear relaxation oscillation of the directly modulated laser (DML) to generate the clock tone. The phenomenon of the clock tone generation by the DML relaxation oscillation is discovered for the first time. Both schemes do not incur extra cost, additional optical components or electrical circuit blocks. In both schemes, the BM clock recovery (CR) circuitry is based on the injection locked oscillator (ILO). Its behavior in the BM-CR application with the input of the distorted non-return-to-zero (NRZ) data is simulated at the system level for the first time. The BM-CR circuitry is designed and fabricated in a standard 0.18 !lm CMOS technology to experimentally demonstrate the two schemes operating at the bit rate close to 10 Gbps. / Thesis / Doctor of Philosophy (PhD)
| Identifer | oai:union.ndltd.org:mcmaster.ca/oai:macsphere.mcmaster.ca:11375/5649 |
| Date | 12 1900 |
| Creators | Yan, Minhui |
| Contributors | Huang, Dr. Wei-Ping, Chen, Dr. Chih-Hung, Electrical and Computer Engineering |
| Source Sets | McMaster University |
| Language | English |
| Detected Language | English |
| Type | Thesis |
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