A unique all-optical 1x2 self-routed switch is introduced. This switch routes an optical packet from one input to one of two possible outputs. The header and payload are transmitted separately in the system, and the header bits are processed in parallel thus increasing the switching speed as well as reducing the amount of buffering required for the payload. A 1x2 switching operation is analysed and a switching ratio of up to 14dB is obtained. The objective of the research was to investigate a unique all-optical switch. The switch works by processing the optical bits in a header packet which contains the destination address for a payload packet. After the destination address is processed the optical payload packet gets switched to one of two outputs depending on the result of the optical header processing. All-optical packet switching in the optical time domain was accomplished by making use of all-optical parallel processing of an optical packet header. This was demonstrated in experiments in which a three bit parallel processing all-optical switching node was designed, simulated and used to successfully demonstrate the concept. The measure of success that was used in the simulated experiments was the output switching ratio, which is the ratio between the peak optical power of a high bit at the first output and the peak optical power of a high bit at the second output. In all experimental results the worst case scenario was looked at, which means that if there was any discrepancy in the peak value of the output power then the measurement’s minimum/maximum value was used that resulted in a minimum value for the switching ratio. The research resulted in an optical processing technique which took an optical bit sequence and delivered a single output result which was then used to switch an optical payload packet. The packet switch node had two optical fibre inputs and two optical fibre outputs. The one input fibre carried the header packet and the other input fibre carried the payload packet. The aim was to switch the payload packet to one of the two output fibres depending on the bit sequence within the header packet. Also only one unique address (header bit sequence) caused the payload packet to exit via one of the outputs and all the other possible addresses caused the payload packet to exit via the other output. The physical configuration of the all-optical switches in the parallel processing structure of the switching node determined for which unique address the payload packet would exit via a different output than when the address was any of the other possible combinations of sequences. Only three Gaussian shaped bits were used in the header packet at a data rate of 10 Gbps and three Gaussian shaped bits in the payload packet at a data rate of 40 Gbps, but in theory more bits can be used in the payload packet at a decreased bit length to increase throughput. More bits can also be used in the header packet to increase the number of addresses that can be reached. In the simulated experiments it was found that the payload packet would under most circumstances exit both outputs, and at one output it would be much larger than at the other output (where it was normally found to be suppressed when compared to the other output’s optical power). The biggest advantage of this method of packet-switching is that it occurs all-optically, meaning that there is no optical to electronic back to optical conversions taking place in order to do header processing. All of the header processing is done optically. One of the disadvantages is that the current proposed structure of the all-optical switching node uses a Cross-Gain Modulator (XGM) switch which is rather expensive because of the Semiconductor Optical Amplifier (SOA). In this method of packet-switching the length of the payload packet cannot exceed the length of one bit of the header packet. This is because the header processing output is only one header bit length long and this output is used to switch the payload packet. Thus any section of the payload packet that is outside this header processing output window will not be switched correctly / Dissertation (MEng (Electronic Engineering))--University of Pretoria, 2007. / Electrical, Electronic and Computer Engineering / unrestricted
| Identifer | oai:union.ndltd.org:netd.ac.za/oai:union.ndltd.org:up/oai:repository.up.ac.za:2263/24848 |
| Date | 24 January 2006 |
| Creators | Ingram, Riaan |
| Contributors | Mrs R Geldenhuys, riaan.ingram@accentive.com |
| Source Sets | South African National ETD Portal |
| Detected Language | English |
| Type | Dissertation |
| Rights | © 2005, University of Pretoria. All rights reserved. The copyright in this work vests in the University of Pretoria. No part of this work may be reproduced or transmitted in any form or by any means, without the prior written permission of the University of Pretoria. |
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