This work is dealing with phase lock loop design. In the theoretical part is principal description. In the practical part is detailed mathematical description, choice of various blocks, design calculation and optimalization of final solution. Designed solution is simulated and final result are commented.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:220085 |
| Date | January 2013 |
| Creators | Hejlek, Pavel |
| Contributors | Háze, Jiří, Prokop, Roman |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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