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Optimization of performance and reliability of HZO-based capacitors for ferroelectric memory applications

In an era in which the amount of produced and stored data continues to exponentially grow, standard memory concepts start showing size, power consumption and costs limitation which make the search for alternative device concepts essential. Within a context where new technologies such as DRAM, magnetic RAM, resistive RAM, phase change memories and eFlash are explored and optimized, ferroelectric memory devices like FeRAM seem to showcase a whole range of properties which could satisfy market needs, offering the possibility of creating a non-volatile RAM.
In fact, hafnia and zirconia-based ferroelectric materials opened up a new scenario in the memory technology scene, overcoming the dimension scaling limitations and the integration difficulties presented by their predecessors perovskite ferroelectrics. In particular, HfₓZr₁₋ₓO₂ stands out because of high processing flexibility and ease of integration in the standard semiconductor industry process flows for CMOS fabrication. Nonetheless, further understanding is necessary in order tocorrelate device performance and reliability to the establishment of ferroelectricity itself. The aim of this work is to investigate how the composition of the ferroelectric oxide, together with the one of the electrode materials influence the behavior of a ferroelectric RAM. With this goal, different process parameters and reliability properties are considered and an analysis of the polarization reversal is performed. Starting from undoped hafnia and zirconia and subsequently examining their intermixed system, it is shown how surface/volume energy contributions, mechanical stress and oxygen-related defects all concur in the formation of the ferroelectric phase. Based on the process optimization of an HfₓZr₁₋ₓO₂-based capacitor performed within these pages, a 64 kbit 1T1C FeRAM array is demonstrated by Sony Semiconductor Solutions Corporation which shows write voltage and latency as low as 2.0 V and 16 ns, respectively. Outstanding retention and endurance performances are also predicted, which make the addressed device an extremely strong competitor in the semiconductor scene.

Identiferoai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:80322
Date04 August 2022
CreatorsMaterano, Monica
ContributorsMikolajick, Thomas, Dubourdieu, Catherine, Technische Universität Dresden
Source SetsHochschulschriftenserver (HSSS) der SLUB Dresden
LanguageEnglish
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/publishedVersion, doc-type:doctoralThesis, info:eu-repo/semantics/doctoralThesis, doc-type:Text
Rightsinfo:eu-repo/semantics/openAccess

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