In this thesis, we study the electrical characteristics of a series of polysilicon thin-film transistors (poly-Si TFTs) with different numbers of multiple channels of various widths, with lightly-doped drain (LDD) structures. Among all investigated TFTs, the nano-scale TFT with ten 67 nm-wide split channels (M10) has superior and more uniform electrical characteristics than other TFTs, such as a higher ON/OFF current ratio (>109), a steeper subthreshold slope (SS) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL) and a suppressed kink-effect. These results originate from the fact that the active channels of M10 TFT has best gate control due to its nano-wire channels were surrounded by tri-gate electrodes. Additionally, experimental results reveal that the electrical performance of proposed TFTs enhances with the number of channels from one to ten strips of multiple channels sequentially, yielding a profile from a single gate to tri-gate structure.
In addition, we have also studied the multi-gate combining the pattern-dependent nickel (Ni) metal-induced lateral crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels. Experimental results reveal that applying ten nanowire channels improves the performance of Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current and a lower threshold voltage (Vth) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multi-gate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low Vth, a steep subthreshold swing (SS) and kink-free output characteristics. The multi-gate with ten nanowire channels NI-MILC TFTs has few poly-Si grain boundary defects, a low lateral electrical field and a gate channel shortening effect, all of which are associated with such high-performance characteristics. The PDMILC TFTs process is compatible with CMOS technology, and involves no extra mask. Such high performance PDMILC TFTs are thus promising for use in future high-performance poly-Si TFT applications, especially in AMLCD and 3D MOSFET stacked circuits.
Otherwise, we have investigated the mechanism of the leakage currents in polysilicon TFT with different temperature and applied biases. Moreover, we have simulated the electric fields in different structure polysilicon TFT to explain the mechanism of the leakage currents. By comparing the leakage currents in different channel structures, the leakage current in nanowire channel structure is higher than that in non-nanowire channel structure. Moreover, the leakage current in multiple gate structure is lower than that in single gate structure. Therefore, these two experimental results are caused by high electric field in the drain-to-gate overlap and drain-to-body depletion region respectively.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0719107-165415 |
| Date | 19 July 2007 |
| Creators | Huang, Po-Chun |
| Contributors | An-Kuo Chu, Ting-Chang Chang, Mei-Ying Chang, Cheng-Tung Huang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719107-165415 |
| Rights | unrestricted, Copyright information available at source archive |
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