The Power Amplifier is the most power-consulting block among the building blocks of RF transceivers. It is still a difficult problem to design power amplifiers, especially for linear, low voltage operation. Until now power amplifiers for wireless applications is being produced almost in GaAs processes with some exceptions in LDMOS, Si BJT, and SiGe HBT. The submicron CMOS processes for power amplifiers are under research focus since CMOS offers integration for power amplifier with rest of the transceivers blocks due to its high yield. Also CMOS process is cheap.
This thesis report details the design process of a class AB power amplifier for GSM wireless applications using 0.35 µm CMOS process. The transmit frequency for GSM-1800 standard for handset applications is 1710 MHz - 1785 MHz. The power amplifier has been designed to deliver 2 W of minimum output power into a 50 Q load. The circuit-was designed and simulations indicated a peak power added efficiency of 47 %.
| Identifer | oai:union.ndltd.org:ucf.edu/oai:stars.library.ucf.edu:rtd-2497 |
| Date | 01 January 2002 |
| Creators | El-Dakroury, Mohamed |
| Publisher | University of Central Florida |
| Source Sets | University of Central Florida |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Retrospective Theses and Dissertations |
| Rights | Written permission granted by copyright holder to the University of Central Florida Libraries to digitize and distribute for nonprofit, educational purposes. |
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