Power Analysis Attacks pose serious threats to hardware implementations of
cryptographic systems. To retrieve the secret key, the attackers can exploit the mutual
information between power consumption and processed data / operations through
monitoring the power consumption of the cryptosystems. Field Programmable Gate Arrays
(FPGA) have emerged as attractive implementation platforms for providing hardware-like
performance and software-like flexibility for cryptosystem developers. These features
come at the expense of larger power consumption, which makes FPGAs more vulnerable
to power attacks. Different countermeasures have been introduced in the literature, but as
they have originally been developed for Application-Specific Integrated Circuits (ASIC),
mapping them onto FPGAs degrades their effectiveness. In this work, we propose a logic
family based on pass transistors, which essentially consists of hardware replication, that can be used to build FPGAs with constant power consumption. Since the power consumption is
no longer related to processed data and operations, a quadruple robustness to attacks based on dynamic power consumption, static power consumption, glitches, and early evaluation effect is achieved. Such a secured-by-design FPGA will relieve the cryptosystems developers from doing advanced analog design to secure the cryptosystem implementation. Our pass-transistor logic family can also be used in implementing ASICs. The silicon area overhead costs are shown to be less than prior art, which makes our FPGA attractive to cryptosystems developers. / Graduate / 2018-07-26
| Identifer | oai:union.ndltd.org:uvic.ca/oai:dspace.library.uvic.ca:1828/8522 |
| Date | 31 August 2017 |
| Creators | Almohaimeed, Ziyad Mohammed |
| Contributors | Sima, Mihai |
| Source Sets | University of Victoria |
| Language | English, English |
| Detected Language | English |
| Type | Thesis |
| Format | application/pdf |
| Rights | Available to the World Wide Web |
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