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Modely tranzistorů technologie CMOS 0.35 um I3T pro PSpice / Models of transistors of CMOS 0.35 um process for PSpice

The master’s thesis focuses on model designing of active components for PSpice simulator. Creation of models are based on text description, which is avaible in Cadence Spectre libraries. The aim of this thesis is approximate conversion of CMOS and bipolar tranzistors based on I3T 0.35 m technology. Simulation’s results and their comparation are discussed below.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:220362
Date January 2014
CreatorsVeverka, Vojtěch
ContributorsDvořák, Radek, Šotner, Roman
PublisherVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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