A multiphase clock generator using single-delay-line phase compensation technique and its application in 1/N-rate clock and data recovery /

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Thesis (Ph.D.)--University of Texas at Dallas, 2007. / Includes vita. Includes bibliographical references (leaves 91-93)

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Identifer	oai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/180139353
Date	January 2007
Creators	Chen, Xu,
Source Sets	OCLC
Language	English
Detected Language	English