This letter discusses a feasible variant of vertically integrated reconfigurable field effect transistors (RFET) based on top-down nanowires. The structures were studied by 3-D device simulations. Subdividing the structure into two vertical pillars allows a lean technological realization as well as simple access to the electrodes. In addition of enabling p- and n-FET operations like a horizontal RFET, the device delivers higher performance. We show that by the integration of additional vertical pillars and select gates, a higher device functionality and flexibility in interconnection are provided.
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:76767 |
| Date | 26 November 2021 |
| Creators | Baldauf, Tim, Heinzig, André, Mikolajick, Thomas, Weber, Walter M. |
| Publisher | IEEE |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | info:eu-repo/semantics/publishedVersion, doc-type:article, info:eu-repo/semantics/article, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | 1558-0563, 10.1109/LED.2018.2847902 |
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