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Komprese videa v obvodu FPGA / Implementation of video compression into FPGA chip

This thesis is focused on the compression algorithm's analysis of MJPEG format and its implementation in FPGA chip. Three additional video bitstream reduction methods have been evaluated for real-time low latency applications of MJPEG format. These methods are noise filtering, inter-frame encoding and lowering video's quality. Based on this analysis, a MJPEG codec has been designed for implementation into FPGA chip XC6SLX45, from Spartan-6 family.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:221010
Date January 2014
CreatorsTomko, Jakub
ContributorsFujcik, Lukáš, Bohrn, Marek
PublisherVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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