The thesis is composed of two different IC design projects, which are briefly introduced as follows.
The first topic is an area-saving decoder structure for ROMs. In this part of work, we propose a novel 3-dimensional decoding method. The stages of address decoding are drastically shortened. Hence, the delay is reduced as well as the power consumption. The overall transistor count and the delay are thoroughly derived. A physical 256x8 ROM using the proposed decoder is fabricated by UMC 0.5 mm 2P2M CMOS technology.
The second part is the NIC (Network Interface Controller) design. The NIC transfers data frames from and to transmitter and receiver buffers in the host memory, respectively. Meanwhile, the transferred data must also comply with the IEEE 802.3 standard. The design is compatible with CSMA/CD type Local Area Network, including 10/100 Mbps Ethernet.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0626100-134230 |
| Date | 26 June 2000 |
| Creators | Chen, Ying-Pei |
| Contributors | Chua-Chin Wang, Sying-Jyan Wang, Ing-Jer Huang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626100-134230 |
| Rights | unrestricted, Copyright information available at source archive |
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